MIPI I3C
The MIPI I3C solution is supported on MSO, TravelLogic 4000, and LA3000+ series models.
The MIPI I3C specification version currently supported is Ver. 1.1.1.
Feature
Protocol Analyzer
Channel:
Set the SCL & SDA channel.
Options:
Trigger On:
The trigger function can trigger an external DSO to capture waveforms from the Trigger-Out port.
- SDR Error:
- TE0/TE1/TE2/TE3/TE4/TE5
- Trigger the 6 types of target error defined in the specification.
- DDR Error:
- CRC/Parity/Preamble
- Trigger the CRC, Parity, and Preamble errors in HDR-DDR mode.
- I3C Packet: Trigger on the Address, CCC, and Data frames in an I3C packet.
Startup I2C Static Address:
Set I2C static address to the I2C devices.
SCL Clock Freq.:
Set the MIPI I3C clock frequency.
Threshold:
Set the trigger level, the range is -6 V ~ 6 V, default is 0.9 V.
Report area:
The Detail window shows the details of MIPI I3C.
The Navigator window shows the statistics of CCC, Target errors, and HDR-DDR errors.
The Hide Items window can show or hide the selected items.
The Statistics list can quickly categorize packets and track their location.
Bus Decode
Channel:
Set the SCL & SDA channel.
Startup I2C Static Address:
Set the I2C static address for the I2C devices.
Note: I2C static address items are stored in the working folder. Default path: C:\Users\User\Documents\Acute\MSO\I3C_StatAddr.bin. This file must accompany the waveform file; copy it into the path above when loading the file.
Color:
Set the background color of packet frame.
Range:
Set the decoded range.
Result:
Trigger
Channel:
Set the SCL & SDA channel.
Timing Violation:
Trigger on a timing violation; the unit is ns.
Simple Trigger:
Trigger the Start/Repeated Start/Stop frame.
Error Trigger:
Trigger the TE0~ TE5 and CRC/Parity/Preamble error in HDR-DDR mode.
Clause Trigger:
Trigger on the Address/CCC/Data frame in a MIPI I3C packet.
Result:
Trigger the TE1 error.
- Trigger the HDR-DDR CCC(20h)
- Trigger the tSU;STO / tCBP = 700 ns timing violation
FAQ
- What MIPI I3C version is supported?
- A: Supports MIPI I3C Version 1.1.1.
- Is MIPI I3C HDR mode supported?
- A: Yes, HDR-DDR, HDR-TSP and HDR-TSL are supported.
- Are target errors defined in MIPI I3C specification supported?
- A: Yes, TE0 ~ TE5 are supported.
- Is Tx supported?
- A: No.