MIPI I3C Trigger (Improved Inter-Integrated Circuit)

MIPI I3C trigger supports Start / Repeat Start / Stop, ACK / NACK, Error Trigger (TE0–TE5, CRC / Parity / Preamble), and Clause Trigger pattern match on Address / CCC / Data.

TravelBus provides special I2C channel options, so the MIPI I3C trigger UI on TravelBus includes an extra channel source. See Settings and Clause Trigger.

Trigger Settings

MIPI I3C Trigger (LA)

MIPI I3C Trigger (TravelBus; extra channel source)

• Channel: I2C Port or LA Port. Default is LA port.
• Simple Trigger: Start of frame / Repeat Start / Stop of frame. Default: all cleared.
• ACK / NACK: Default: both cleared.
• Error Trigger: SDR TE0–TE5; DDR CRC / Parity / Preamble. Field enabled (Enable) when selected. Default: all cleared.
• Clause Trigger: See Clause Trigger.
• State: Address / Common Command Code (CCC) / Data; enter a data pattern; XXh = Don't care.
  • Offset: Any Offset (Default; first matching I3C data) / Fixed Offset (byte position; offset 0 = first byte).
  • RSTDAA (06h) / ENTDAA (07h): Event 1 CCC = RSTDAA / ENTDAA; Event 2 with ENTDAA requires 9-bit data and Fixed Offset.
  • EHTHDR0 (20h) / EHTHDR1 (21h) / EHTHDR2 (22h) HDR Data: 16-bit payload format.

Trigger on RSTDAA / ENTDAA data (Event 1)

ENTDAA 9-bit data (Fixed Offset)

EHTHDR0 / 1 / 2 HDR Data (16-bit payload)

See also

• MIPI I3C — Protocol Analyzer settings
• MIPI I3C — Measurement guide