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RMII (Reduced MII)

What is RMII?

Overview

RMII (Reduced Media Independent Interface) is a pin-reduced variant of MII developed by a consortium of semiconductor companies in 1998 to address the growing pin count constraints in embedded systems. RMII reduces the pin count from 16 (MII) to just 7 by using a 2-bit wide datapath instead of 4-bit, and by using a single shared 50 MHz reference clock instead of separate TX and RX clocks. Despite the reduced pin count, RMII maintains full compatibility with 10/100 Mbps Ethernet operation, making it ideal for cost-sensitive embedded applications.

The key innovation in RMII is the shared 50 MHz reference clock (REF_CLK) that is used by both the MAC and PHY for transmit and receive operations. This clock is typically generated by an external oscillator and distributed to both chips, though some PHYs can generate it internally. The 2-bit datapath operates at 50 MHz continuously, providing 100 Mbps throughput (2 bits × 50 MHz = 100 Mbps) for Fast Ethernet, with 10 Mbps mode implemented by repeating each dibit 10 times.

RMII has become extremely popular in microcontroller-based Ethernet designs, particularly in ARM Cortex-M and similar embedded processors where pin count is at a premium. Most modern Ethernet PHYs support both MII and RMII modes, often selectable via configuration pins or registers. The reduction from 16 to 7 pins (56% reduction) provides significant cost savings in PCB routing complexity and package costs without sacrificing functionality.

Technical Specifications

Data Interface

  • Data Width: 2 bits (dibit) per direction
  • Clock Frequency: 50 MHz fixed (for both 10 and 100 Mbps)
  • Pin Count: 7 data/control signals (plus 2 management = 9 total)
  • Throughput: 10/100 Mbps
  • Clocking: Single REF_CLK shared by TX and RX

Signal Description

TX Signals (MAC to PHY - 3 signals) - TXD[1:0]: Transmit data (2-bit bus) - TX_EN: Transmit enable (active high during frame transmission)

RX Signals (PHY to MAC - 4 signals) - RXD[1:0]: Receive data (2-bit bus) - CRS_DV: Carrier sense / receive data valid (combined signal) - RX_ER: Receive error (indicates PHY detected error)

Clock (1 signal - bidirectional) - REF_CLK: 50 MHz reference clock (typically external oscillator)

Management Interface (2 signals - same as MII) - MDC: Management data clock (up to 2.5 MHz, sourced by MAC) - MDIO: Management data I/O (bidirectional serial data)

CRS_DV Signal

The CRS_DV signal is a unique feature of RMII that multiplexes two functions: - During reception: Acts as RX_DV (receive data valid) - When not receiving: Acts as CRS (carrier sense) - Logic: CRS_DV = RX_DV OR CRS - This multiplexing saves one pin compared to MII

Timing Characteristics

Clock Specifications - Frequency: 50 MHz ±50 ppm (very tight tolerance) - Duty Cycle: 50% ±5% - Jitter: <1 ns RMS recommended - Source: External 50 MHz oscillator (25 MHz × 2 PLL in some PHYs)

Data Timing (typical values) - Setup Time: 4 ns minimum (data to REF_CLK rising edge) - Hold Time: 2 ns minimum (data after REF_CLK rising edge) - Clock-to-Output: 14 ns maximum (PHY driving RXD, CRS_DV, RX_ER) - Propagation Delay: Matched within 5 ns

Speed Modes - 100 Mbps: Data changes every REF_CLK cycle (2 bits/cycle × 50 MHz = 100 Mbps) - 10 Mbps: Each dibit repeated 10 times (stretches 100 Mbps timing by 10×)

RMII Advantages

Pin Count Reduction - 7 signals vs. 16 for MII (56% reduction) - Smaller packages possible - Lower BOM cost - Simplified PCB routing

Single Clock Domain - One 50 MHz REF_CLK for entire interface - No clock domain crossing issues - Simplified timing analysis - Easier to implement in FPGAs/ASICs

Power Efficiency - Lower I/O count reduces power - Single clock distribution - Well-suited for battery-powered devices

PCB Layout Benefits - Fewer traces to route - Less complex signal integrity management - Smaller connector footprint - Easier ground plane management

Decoder Configuration

When analyzing RMII with a logic analyzer, configure the following:

Signal Connections

Minimum Configuration (data only - 7 channels) - TXD[1:0] - 2 channels - TX_EN - 1 channel - RXD[1:0] - 2 channels - CRS_DV - 1 channel - RX_ER - 1 channel

With Clock (8 channels - recommended) - Add REF_CLK - 1 channel

With Management (10 channels total) - Add MDC and MDIO - 2 channels

Sampling Requirements

  • Minimum Sample Rate: 250 MS/s (5× the 50 MHz clock)
  • Recommended: 500 MS/s to 1 GS/s for clean captures
  • Critical: Must sample REF_CLK for proper decoding

Decoder Parameters

  • Interface Type: RMII
  • Reference Clock: 50 MHz
  • Speed: Auto-detect from dibit repetition (10 vs 100 Mbps)
  • Clock Edge: Rising edge (standard for RMII)
  • Frame Format: Ethernet II (DIX) or IEEE 802.3
  • CRS_DV Decoding: Enable to separate RX_DV and CRS functions
  • Error Detection: Enable RX_ER monitoring
  • FCS Validation: Enable CRC checking

Display Options

  • Show TX and RX data separately with timestamps
  • Display Ethernet frame fields
  • Highlight TX_EN and CRS_DV active periods
  • Indicate errors via RX_ER or CRC failures
  • Show CRS_DV interpretation (RX_DV vs CRS)
  • Decode MDIO register reads/writes
  • Display speed mode (10 or 100 Mbps)

Trigger Settings

  • Frame Start: Trigger on TX_EN or CRS_DV rising edge
  • Specific Address: Trigger on MAC address pattern in TXD or RXD
  • Error Events: Trigger on RX_ER assertion
  • MDIO Activity: Trigger on MDC/MDIO start condition
  • Clock Reference: Use REF_CLK as external clock input if analyzer supports it

Analysis Tips

  1. Verify REF_CLK
  2. Must be exactly 50 MHz (±50 ppm)
  3. Check duty cycle (50% ±5%)
  4. Measure jitter (should be <1 ns RMS)

  5. Verify all devices receive clean clock

  6. Identify Speed Mode

  7. 100 Mbps: Data changes every REF_CLK cycle
  8. 10 Mbps: Each dibit repeats 10 times

  9. Look for repetition pattern in RXD/TXD

  10. CRS_DV Interpretation

  11. During frame reception: CRS_DV = RX_DV
  12. Between frames: CRS_DV = CRS
  13. Should go high with first preamble bit

  14. Remains high through FCS

  15. Check Frame Structure

  16. Preamble nibbles: 0x5, 0x5, 0x5.. (in 2-bit chunks: 01, 01, 01..)
  17. SFD nibbles: 0x5, 0xD

  18. Normal Ethernet frame structure follows

  19. Timing Validation

  20. Data setup/hold relative to REF_CLK rising edge
  21. TX_EN timing around data
  22. CRS_DV timing around data

  23. Inter-frame gap: minimum 96 bit times (19.2 µs at 100 Mbps)

  24. Common Waveform Patterns

  25. 100 Mbps: Busy data changes on every clock
  26. 10 Mbps: Data appears "stretched" with repetitions
  27. Idle: CRS_DV low, TXD and RXD may be undefined

Common Issues

REF_CLK Problems - Symptom: No communication, PHY not functioning - Cause: Missing or wrong frequency REF_CLK - Solution: Verify 50 MHz oscillator is running, check PHY REF_CLK input

Clock Tolerance Issues - Symptom: Intermittent errors, lost frames - Cause: REF_CLK frequency outside ±50 ppm tolerance - Solution: Use crystal oscillator (not ceramic resonator), verify frequency accuracy

Timing Violations - Symptom: Intermittent CRC errors - Cause: Setup/hold violations, excessive trace length or skew - Solution: Minimize trace lengths, match trace lengths, improve signal integrity

Speed Mode Confusion - Symptom: 10 Mbps not working properly - Cause: MAC not repeating dibits 10 times - Solution: Verify MAC implementation, check PHY speed configuration

CRS_DV Misinterpretation - Symptom: False carrier detection or missed frames - Cause: Incorrect understanding of CRS_DV multiplexing - Solution: Decoder must separate RX_DV (during frames) from CRS (between frames)

PHY Mode Selection - Symptom: Interface not working at all - Cause: PHY in MII mode instead of RMII mode - Solution: Check PHY configuration pins or registers, verify RMII mode enabled

Power Sequencing - Symptom: REF_CLK present but no communication - Cause: PHY powered up before REF_CLK stable - Solution: Ensure REF_CLK stable before PHY power-up or release from reset

Design Considerations

REF_CLK Source Selection

  1. External Oscillator (most common)
  2. Dedicated 50 MHz crystal oscillator
  3. Distributed to both MAC and PHY
  4. Best clock quality and stability

  5. Adds component cost

  6. PHY-Generated (some PHYs support)

  7. PHY generates 50 MHz from 25 MHz crystal
  8. Outputs REF_CLK to MAC
  9. Reduces external component count

  10. Verify PHY supports this mode

  11. MAC-Generated (rare)

  12. MAC generates 50 MHz
  13. Outputs REF_CLK to PHY
  14. Uncommon implementation
  15. Check MAC capability

PCB Layout Guidelines - Keep REF_CLK trace short and direct - Match data trace lengths within 1 inch - Maintain impedance control (50Ω single-ended typical) - Route away from noise sources - Use solid ground plane - Terminate unused inputs per datasheet

Reference

Last Updated: 2026-02-02

See also