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SPI (Serial Peripheral Interface)

SPI (Serial Peripheral Interface) is a synchronous serial interface, commonly 4-wire (SCK / CS / SDI / SDO), and also available as 3-wire or 2-wire. Data is clocked with SCK.

Mismatch in SPI Type, Bit Order, or Word Size yields misaligned or wrong data. Without CS (Unused Chip Select), set Clock Idle correctly to separate frames. For channel-prefix differences, see Settings.

Decode Settings

Decode Settings

SPI Decode Settings
  • SPI Type: Wiring mode. Default: 3 Wire-SPI (with Chip Select).
    • 4 Wire-SPI: Uses SCK, CS, SDI, and SDO. CS: Active High / Active Low; SDI / SDO: Rising / Falling. Display: SDI only / SDO only / Both. Defaults for this type: CS = Active High, SDI = Rising, SDO = Falling, display = Both.
    • 3 Wire-SPI: Uses SCK, CS, and one Data line. Check SDI(Write)-Waiting-SDO(Read) for half-duplex bit counts. Defaults for this type: CS = Active Low, Data = Rising; half-duplex cleared (write / read / wait bits often 8 / 8 / 2).
    • 3 Wire-SPI (Unused Chip Select): Uses SCK, SDI, and SDO without CS. Set Clock Idle to separate frames. Display: SDI only / SDO only / Both. Defaults for this type: SDI / SDO = Rising, display = Both, Idle = 300 ns.
    • 2 Wire-SPI (Unused Chip Select): Uses SCK and SDA without CS. Set Clock Idle. Defaults for this type: Data = Rising, Idle = 300 ns; half-duplex cleared.
  • Clock Channel (SCK): Assign the clock channel.
  • Use External clock: Use an external clock. Field enabled (Enable) when checked. Default: cleared.
  • Bit Order: LSB First / MSB First. Default: MSB First.
  • Word Size: Bits per data word (4–40). Default: 8.
  • Data valid from SCK: Sample delay from the SCK edge (0–3 sample points). Default: 0 (no delay).
  • Report:
    • Show Idle state in report window: Show Idle in the report. Field enabled (Enable) when checked. Default: checked.
    • Reduce report: Compact the report. Field enabled (Enable) when checked. Default: cleared.
    • Show data in report (Column): Data columns in the report (1–16). Default: 16.

4 Wire-SPI

4 Wire-SPI

3 Wire-SPI

3 Wire-SPI (with Chip Select; half-duplex optional)

3 Wire unused CS

3 Wire-SPI (Unused Chip Select)

2 Wire unused CS

2 Wire-SPI (Unused Chip Select)

Without CS, when Idle ≠ 0, a clock pause longer than Idle separates frames:

Idle separation

Unused Chip Select: frame separation by Clock Idle

Idle = 0 treats the stream as continuous data:

Idle zero

Unused Chip Select: Idle = 0 (continuous data)

Result

SPI Result

SPI decode result

See also