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BiSS (Bidirectional Serial Synchronous)

BiSS, from iC-Haus, is an open point-to-point synchronous serial interface for absolute encoders. The master drives the clock on MA and the slave returns data on SLO. There is no chip select, so each frame is delimited by the gap after the clock stops. Both BiSS-C and BiSS-B are supported.

Besides the position data (Single Cycle Data), BiSS carries a slow bidirectional control channel for register access. It borrows one bit from every frame — CDM on the master side, CDS on the slave side — so one register transaction spans dozens of frames. Choose which side to inspect with Mode.

See Settings for channel prefixes.

Decode Settings

Decode Settings

BiSS Decode Settings
  • MA / SLO: Assign the clock (MA) and data (SLO) channels.
  • Mode: Single Cycle Data (SCD) for position data, or Register Access - Master (CDM) / Register Access - Slave (CDS) for the control channel. Default: Single Cycle Data (SCD).
  • Data Channel: Number of data blocks in one frame. Default: 1.
  • Serial Data Length (bits): Total position data length, 1 ~ 64. With Auto checked the length is detected from the waveform and the field is read-only; clear it to enter the value by hand. Default: Auto.
  • Alignment (bits): Alignment bits appended after the position data. Default: 0.
  • Combine Multi-Turn and Single-Turn: Show the position as one value instead of two. Default: cleared.
  • Single-Turn(ST): Single-Turn bit count. Multi-Turn(MT) takes the remaining bits and is shown beside it. Default: 8.
  • CRC Bit amount / CRC Polynomial / CRC Initial Value: Sensor CRC parameters. The BiSS specification does not fix them, so set them from the encoder datasheet. Defaults: 6 / 0x43 / 0x0.
  • Protocol: BiSS-C or BiSS-B. BiSS-B has no CDS bit and its status-bit polarity is inverted. Default: BiSS-C.
  • SLO Phase (samples): Shift the SLO sampling point when the data is skewed against the clock. Default: 0.
  • Register Data Columns: Data bytes per row in the register report, 8 or 16. Default: 8.

Result

BiSS Result

BiSS-C Single Cycle Data decode result

A register transfer spans dozens of BiSS frames; the decode assembles it into one row:

BiSS Result

Register Access - Slave (CDS): one sequential read of five bytes

See also