HyperBus Trigger
HyperBus trigger supports Start of frame and Clause Trigger pattern match on Command / Address and Data. Set bus width, Mode, and Latency to match the bus.
See Settings and Clause Trigger.
Trigger Settings
- Channel: Assign CS, CLK, RWDS1 / RWDS2, and Data (channel indices omitted).
- Using CLK to latch Read Data: Latch read data with CLK. Related options are enabled (Enable) when checked.
- DATA width: x8 / x16. Default: x16.
- Quick set / User Defined: Batch-assign Data channels or set each bit manuallyUser Defined.
- Settings: Data Arrangement format (popup).
- Invert CLK / Invert RWDS: Invert CLK or RWDS1 / 2. Field enabled (Enable) when checked.
- Mode: Hyper Flash / Hyper RAM. Default: Hyper Flash.
- Latency: Latency sample-point count. Default: 7.
- CMD / Write CLK Delay, Read CLK / RWDS Delay: Delay timing.
- Simple Trigger: Start of frame. Field enabled (Enable) when checked.
- Clause Trigger: See Clause Trigger.
- State: Enter Command / Address bits and Data as a data pattern; unused fields XX = Don't care.
- Command / Data: Default each field XX.
- Offset: Any Offset / Fixed Offset. Default: Any Offset, offset 0. Fixed Offset enables (Enable) the offset field.