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Serial Flash / SPI NAND Trigger

Serial Flash / SPI NAND trigger supports CS Glitch, tSHSL / tCLQV, and Clause Trigger pattern match on Command / Address / Data (including Dummy Cycles and fixed offset).

Open from the toolbar “Serial Flash protocol trigger”. See Settings and Clause Trigger.

Trigger Settings

Serial Flash Trigger

Serial Flash / SPI NAND Trigger Settings
  • Channel: 4–6 channels depending on mode (CS / CLK / Data / AUX, etc.).
  • CS Glitch Trigger: Trigger on CS glitches; parallel to clause conditions (whichever fires first). High Pulse / Low Pulse; step 0.625 ns, max 80 ns. Default slider index is 1.
  • tSHSL / tCLQV: Adjust sliders to match device timing; unchecking tSHSL field-disables (Disable) that check. Wrong tCLQV can break Data-field matching. Default: tSHSL checked (minimum slider); tCLQV 8.75 ns.
  • Clause Trigger: See Clause Trigger.
  • State: Choose operating mode with the slider (Single / Dual / Quad / Octal, etc.); enter Command, Address, Data as a data pattern; XXh / X = Don't care. Enable fixed Data offset and set the start position (e.g. offset 0 with FFh XXh XXh XXh → Data0 = FFh, others any). Align the Dummy Cycles slider to the waveform (e.g. 8 clocks). Conditions can switch to NOT (NOT allows two Command values).