NAND Flash Trigger
NAND Flash trigger supports channel and data-width setup, Startup Mode, tREA / tDQSQ, commands accepted during busy, Busy time check, and Clause Trigger pattern match on Address / Command / Data.
See Settings and Clause Trigger.
Trigger Settings
- Channel: CLE, ALE, RE, WE, CE, R/B, DQS; optional Reverse RE / Reverse DQSchecked; Reverse RE / Reverse DQS cleared.
- DATA: x8 / x16. Default: x8.
- Quick Setup: Set LSB only; software assigns the rest (e.g. LSB = B0 → MSB = B7; LSB = B7 → MSB = B14). Default: checked.
- User Defined: Open the popup to assign each data bit manually.
- Startup Mode: For DDR Command / Address / Data, check DQS and Toggle / ONFI DDR Mode; ignore for SDR. Default: Init DDR cleared.
- tREA / tDQSQ: Read data is sampled after an edge delay—tREA in SDR, tDQSQ in DDR. Default: tREA 20 ns (slider 200); tDQSQ 500 ps (slider 5).
- Commands accepted during busy: Commands that may still trigger while Busy time check is active. Default: checked; commands 70h / FFh / 78h / 7Bh (others XXh). Leave blank to ignore commands during busy.
- Busy time check: Check and open Setting…. Default: cleared. Up to 6 groups, 4 commands each; fires when Busy time ≥ set value.
- Clause Trigger: See Clause Trigger.
- State: Enter Address, Command, Data as a data pattern; XXh / X = Don't care.
Time between cursors T and A is tREA:
Time between cursors T and A is tDQSQ:
Commands accepted during busy popup:
Trigger on Command 70h while busy:
Busy time check popup (example: Command 10h and Busy time ≥ 25 µs):